The present invention relates generally to integrated circuits and more particularly to on-chip silicon-based inductors.
Increasing demands for personal mobile communications equipment have motivated recent research activities to focus on the development of inexpensive, small size, low power consumption, and low noise level systems. To satisfy these requirements, one of the most important and indispensable circuit components is the on-chip silicon-based inductor.
As a result, miniaturization of the inductor on silicon has become a current key research area and extensive work has been done in this area. However, despite efforts by many researchers having skill in the art, achieving high performance on-chip inductors, i.e., high qualify factor (Q), still remains a major problem especially when radio frequency integrated circuits (RFICs) are built on silicon.
Conventional inductors built on silicon are generally planar in nature. The current complementary metal oxide semiconductor (CMOS) process uses a very conductive substrate. Spiral inductors fabricated on such a lossy substrate suffer from high capacitive and magnetic losses.
In addition, high dynamic resistance of metal lines at GHz frequency ranges further degrades the inductor performance in CMOS technology as compared to those fabricated in monolithic microwave integrated circuits (MMICs).
Many fabricating techniques, processes, and materials have been proposed to improve the performance of on-chip inductors. Tedious processing techniques such as etching away the silicon substrate under the inductor have been introduced to remove the substrate parasitic effects completely. Despite achieving good results, industries are reluctant to adopt such a technique because of reliability issues such as packaging yield, as well as long-term mechanical stability.
Another approach to minimize the substrate loss for silicon-based inductors has been to increase the substrate resistivity. This technique has yielded significant results, however, the substrate becomes unsuitable for building active MOS devices.
The most critical factor hindering the performance of silicon-based inductors is the high resistive aluminum-copper (AlCu) interconnects used in silicon processes.
In comparison, thicker and less resistive gold (Au) metalization together with lossless substrate in gallium arsenide (GaAs) technology permits high performance inductors to be fabricated easily. To overcome high metalization resistance, a popular technique is to have the layers of metal stacked together, thereby achieving a high Q inductor.
Another possible alternative is to use an active inductor. In an active inductor high Q factor and inductance can be achieved in a really small silicon area. However, such approach suffers from high power consumption and high noise levels that are not acceptable for low power and high frequency applications. In addition, performance of active inductors are very sensitive and dependent upon the inductor""s biasing circuitry, making it time consuming and tedious to design.
As a result of the above, the simplest and most commonly used on-chip inductors are planar silicon-based spiral inductors, which require careful layout optimization techniques to improve performance.
In the conventional spiral inductor design, the inductor is planar and fabricated on a conductive silicon substrate. To improve the Q factor of the spiral inductors, the top metal is usually stacked with a few layers of lower metal through vias to minimize the overall metal series resistance. Nevertheless, when more layers are used to realize a very thick conductor, the whole spiral is brought closer to the substrate. This increases the spiral-to-substrate parasitic capacitance and hence results in a degradation of Q factor as well as the inductor""s self-resonant frequency. Nevertheless, improvement and quality factors are still observed for a 4-layer stacked inductor at 2.45 gigahertz (GHz).
The above technique to improve the inductor""s quality factor is well known and very popular in the industry since it involves no modification to the existing CMOS process flow. Currently, parallel inductors have never been explored because those skilled in the art expect the performance of such parallel inductors to be very poor. For a 2-metal-layer parallel inductor, its conductor parasitic resistance, especially high dynamic resistance at gigahertz frequencies will decrease by 50%. This helps improve the inductor""s Q factor but its resultant inductance will also be lower by 50%. In typical planar parallel inductors, the advantage over the conventional spiral inductor is that vias required for the underpass center conductor connection can be omitted and this greatly reduces the conductor""s series resistance; i.e., the inductors are planar, open, concentric rings which are commonly connected at their open ends. Comparing the inductance and Q factor of a conventional circular inductor (3-turn) and a planar parallel inductor, it was observed that by connecting the turns in a planar-parallel manner to form the spiral reduces the conductor""s series resistance, thereby giving a higher Q factor. However, the inductance produced is very low compared to the conventional design. Therefore, the inductive behavior of such parallel inductors is expected by those skilled in the art to be unsatisfactory and this as been found to be the case.
Solutions to these problems have been long sought, but have long eluded those skilled in the art.
A parallel spiral stacked inductor and manufacturing method therefore is provided. A substrate has a plurality of turns in a plurality of levels, the plurality of turns having a center proximate and a center distal ends. A first plurality of vias connecting the center proximate ends of the plurality of turns and a second plurality of vias connecting the center distal ends of the plurality of turns. A first connecting portion connects to the center proximate ends of the plurality of turns and a second connecting portion connecting to the center distal end of the plurality of turns. A dielectric material contains the inductor.
The present invention provides a stacked parallel inductor wherein the performance is comparable if not better than the conventional stacked inductor. Despite achieving low inductance when metal strips are laid out in a parallel manner, Q factor of the inductor improves by a significant 30%. Hence, if metal strips can be connected in a parallel manner without affecting the overall inductance, such parallel inductors show tremendous potential in replacing the conventional stacked spiral inductors.
The present invention further provides an alternative, if not better solution, to replace the conventional stacked spiral inductor. The planar parallel inductor yields unsatisfactory results. Its low inductance can be overcome in the stacked parallel design. The layout of the parallel spiral conductors allows performance of parallel inductors to be comparable to conventional stacked inductors. The inductor of the present invention is achieved when vias along conductors of the conventional stacked inductor are removed. This means only the regions at the two ends of the metal layers making up the main spiral are connected with vias.
It has been found that even though conductors are electrically connected in parallel, the inductance value is not reduced as in the case of a planar parallel inductor. The stacked parallel inductor has a much higher inductance value compared to the parallel inductor because of the presence of mutual coupling between adjacent conductors. Since the conductors are stacked on top of each other, the large conductor surface areas as well as the thin inter metal dielectric promote a significant constructive mutual coupling effect. Hence, mutual inductance generated through this strong coupling compensates for the reduction in self-inductance of the metal lines when they are connected in a parallel fashion. The Q factor for the new design is observed to be slightly higher than the conventional stacked inductor at all frequencies.